Live on March 26 at 9:30 AM Pacific

AI‑Designed Computer System — Board Bring‑Up

Quilter will publicly validate an AI‑designed computer system through live board bring‑up, starting at power‑on and proceeding through real workload execution.
No slides. No demo. No edits.

Reinforcement learning for designing electronics hardware that works.

custom circuit board

Board bring‑up is where hardware designs confront reality. Power integrity, signal behavior, layout decisions, and schematic assumptions are tested by the physical system—not by simulations or screenshots.

In this session, Quilter will repeat the bring‑up and validation process used during Project Speedrun, using the same design and the same constraints. The system will be powered on live and taken through system initialization, operating system bring‑up, and sustained workload execution.

If issues arise, they will be addressed in real time.

Project Speedrun →

Agenda

01

Finding a manufacturing partner

  • Replicating the NXP i.MX 8M Mini EVK as a baseline
  • Working through reference file issues: format translation, file age, and supply chain
  • DFM, DFA, and stackup alignment across manufacturers

02

Baselining with working NXP copies from Sierra

03

Walkthrough of Quilter SOM and baseboard candidates

04

Final designs in Altium

05

Live board bring-up

  • NXP SOM with our baseboard
  • NXP baseboard with our SOM
  • Our SOM and baseboard together
  • PSU measurements
  • Firmware loading using NXP factory tools
  • Linux image boot
  • Hardware validation
  • Weston desktop and NXP GPU demos
  • GNOME desktop

06

Q&A

Meet Your Host

Ben Jordan

Staff Electrical Engineer, Quilter

Ben is a Computer Systems Engineer with a Bachelor of Engineering (Honors I) from USQ, Australia, and is an IPC CID+ certified advanced PCB designer.  Ben brings more than two decades of experience in Electronics Design Automation and system-level electronics hardware engineering to Quilter, including High Speed Digital, Audio, RF/µWave, Power Electronics and Signal/Power Integrity Analysis.

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By Design Type

Test Fixtures & Harnesses

Shave 4–6 weeks off board bring-up

IC Evaluation Boards

Cuts layout cycles from weeks to hours; enables rapid, fabrication-ready design iteration

Design Validation Boards

Shrinks validation cycles from months to days

Backplane & Interconnect Boards

From 30+ days to under 24 hours

By Industry

Semiconductors

Bring-up ready in a single workday (first candidates often appear within the first hour).

Robotics

Compress board bring-up from 4 weeks to under 1 day

Consumer Electronics

Boards ready in a single workday (first candidates often appear within the first hour)

Aerospace & defense

Faster board bring-up for validation and TRR

By Role

R&D managers

Accelerate board bring-up

PCB Designers

Full fab-ready designs in under 4 hours

Electrical engineers

Schematic to fab-ready in under 4 hours

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